Contact-dominated localized electric-displacement-field-enhanced pressure sensing.

Pressure sensors, especially the typical capacitive sensors that feature low power consumption, have drawn considerable interest in emerging and rapidly growing fields such as flexible electronics and humanoid robots, but often suffer from limited performance. Here, we report a contact-dominated design for capacitive pressure sensors to dramatically improve the sensing response and linearity over a broad pressure range. This design is implemented by utilizing hierarchical microstructured electrodes made of robust conductive composites with metallic coverage and layered dielectrics with high unit-area capacitance to realize localized electric-displacement-field-enhanced capacitance change.

Large-scale complementary carbon nanotube integrated circuits for harsh radiation environments.

Silicon-based integrated circuits operating in radiation environments require additional and complex hardening configurations, leading to performance lags compared to the International Roadmap for Devices and Systems. Carbon nanotubes (CNTs), with their ultrastrong chemical bonds and nanoscale dimensions, offer substantial potential for high-performance, radiation-tolerant electronics. However, the challenges associated with radiation-tolerant fabrication processes have hindered the development of macroelectronics using complementary CNT transistors (CNTFETs).

Reconfigurable single-walled carbon nanotube ferroelectric field-effect transistors.

Reconfigurable devices have garnered significant attention for alleviating the scaling requirements of conventional complementary metal-oxide-semiconductor technology by reducing the number of components needed to construct functional circuits. Prior work required continuous voltage application to programming gate terminal(s) alongside the primary gate, undermining the advantages of reconfigurable devices in achieving compact and power-efficient integrated circuits. Here, we realize scalable reconfigurable devices based on single-gate field-effect transistors that integrate highly aligned single-walled carbon nanotube channels with a ferroelectric aluminum scandium nitride gate dielectric.

Two-dimensional indium selenide wafers for integrated electronics.

Two-dimensional (2D) indium selenide, with its low effective mass, high thermal velocity, and exceptional electronic mobility, is a promising semiconductor for surpassing silicon electronics, but grown films have not achieved performance comparable with that of exfoliated micrometer-scale flakes. We report a solid‒liquid‒solid strategy that converts amorphous indium selenide films into pure-phase, high-crystallinity indium selenide wafers by creating an indium-rich liquid interface and maintaining a strict 1:1 stoichiometric ratio of indium to selenium. The as-obtained indium selenide films exhibit exceptional uniformity, a pure phase, and a high crystallinity across an entire ~5-centimeter wafer.

A Novel Time-Division Multiplexing Architecture Revealed by Reconfigurable Synapse for Deep Neural Networks.

Deep learning's growing complexity demands advanced AI chips, increasing hardware costs. Time-division multiplexing (TDM) neural networks offer a promising solution to simplify integration. However, it is difficult for current synapse transistors to physically implement TDM networks due to inherent device limitations, hindering their practical deployment in modern systems.

Complementary Metal-Oxide-Semiconductor Integrated Circuits Based on Aligned Carbon Nanotubes.

Low-dimensional semiconductors have been extensively studied for constructing ultrascaled and high-performance transistors for potential application in digital integrated circuits (ICs) in sub-1 nm technology nodes. Many ICs on various nanomaterials have been continuously demonstrated, but few works have presented both high performance and a complementary metal-oxide-semiconductor (CMOS) architecture, which are necessary for forming ultralarge-scale digital ICs. In this work, we fabricated symmetric CMOS field-effect transistors (FETs) on aligned semiconducting carbon nanotubes (A-CNTs) with high performance and a high yield.

Micro-LED Microdisplays Driven by Carbon Nanotube Active-Matrix Backplanes.

Micro-light-emitting-diodes (μLEDs) are poised to revolutionize flat-panel display (FPD) technology with their exceptional brightness, contrast ratio, energy efficiency, and ultrahigh resolutions, making them indispensable for augmented reality (AR) and virtual reality (VR) microdisplays. However, the realization of high pixel-per-inch (PPI) μLED microdisplays demands advanced thin-film transistor (TFT) backplanes with robust driving capabilities. Presently, single-crystalline silicon CMOS dominates the industry for this application, but its nontransparent nature, wafer size limitations, and high fabrication cost restrict its scalability.

Reconfigurable Flexible Complementary Circuits Based on Polarity-Configurable Carbon Nanotube Transistors.

Functional configurability is highly desired for flexible electronics to serve ever-changing and diverse application scenarios. In complementary metal-oxide-semiconductor (CMOS) logic circuits, functional configurations can be achieved at the most basic device level by modulating the P/N polarity of the field-effect transistors. The intrinsic ambipolarity of low-dimensional materials provides the possibility of configuring the polarity of the constructed transistors by selectively injecting carriers on demand with proper methodologies.

Super-saturated complementary carbon nanotube transistors with intrinsic gain singularities.

Digital-driven scaling poses significant problems to analog circuits because scaling severely deteriorates transistor current saturation, significantly degrading the intrinsic gain. Special material properties of emerging low-dimensional semiconductors trigger the possibility of providing solutions. We report complementary carbon nanotube thin-film transistors with negative differential resistance-induced current super-saturation for high, exponentially variable intrinsic gain with immunity against degradation during scaling.

Self-Anchoring Process to Construct Highly-Aligned-Carbon Nanotube Transistors.

Carbon nanotube (CNT) integrated circuit has recently achieved significant breakthroughs in aligned CNTs (A-CNTs) purity and density, driving notable improvements in transistor on-state performance and integration density. However, the performance of A-CNT transistors remains critically constrained by nanotube mutual stacking and aggregation during field effect transistors (FETs) fabrication, which results in degraded off-state performance in short-channel FETs. In this study, we propose an innovative self-anchoring process (SAP), yttrium oxide (YO) sacrificial layer anchoring in wet clean, and source-drain electrodes anchoring in lift-off, to fabricate the highly aligned-CNT FETs, effectively suppressing CNT stacking during fabrication.

Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration.

Innovations in device architectures and materials promote transistor miniaturization for improved performance, energy efficiency and integration density. At foreseeable ångström nodes, a gate-all-around (GAA) field-effect transistor based on two-dimensional (2D) semiconductors would provide excellent electrostatic gate controllability to achieve ultimate power scaling and performance delivering. However, a major roadblock lies in the scalable integration of 2D GAA heterostructures with atomically smooth and conformal interfaces.

Regulation of Reaction Pathways in Coordinated Chains by Directional Mechanical Force.

Mechanochemistry refers to chemical reactions induced by mechanical forces. Due to different reaction mechanisms, products obtained through mechanochemistry can be distinct from those produced by thermochemistry and photochemistry. Scanning probe microscopy is a powerful tool for studying single-molecule mechanochemical processes.

Ultralow Power Cold-Fuse Memory Based on Metal-Oxide-CNT Structure.

One-time programmable (OTP) memory is an essential component in chips, which has extremely high security to protect the stored critical information from being altered. However, traditional OTP memory based on the thermal breakdown of the dielectric has a large programming current, which leads to high power consumption. Here, we report a gate tunneling-induced "cold" breakdown phenomenon in carbon nanotube (CNT) field-effect transistors, and based on this we construct a "cold" fuse (C-fuse) memory where applying a mild gate voltage can break down the CNT channel without damaging the gate dielectric.

High-performance ternary logic circuits and neural networks based on carbon nanotube source-gating transistors.

Multi-valued logics (MVLs) offer higher information density, reduced circuit and interconnect complexity, lower power dissipation, and faster speed over conventional binary logic system. Recent advancement in MVL research, particularly with emerging low-dimensional materials, suggests that breakthroughs may be imminent if multistates transistors can be fabricated controllably for large-scale integration. Here, a concept of source-gating transistors (SGTs) is developed and realized using carbon nanotubes (CNTs).

High-Performance Dual-Gate Transistors Based on Aligned Carbon Nanotubes.

Aligned carbon nanotubes (A-CNTs), with atomic-scale thickness and ultrahigh carrier mobility, hold promise for constructing future sub-1 nm node integrated circuits (ICs) with higher speed and lower power consumption. However, the fabricated A-CNT transistors often suffer from the disorder of high-density CNT, which degrade the off-characteristic deviating significantly from theoretical values. Introducing a dual-gate (DG) configuration can provide higher gate control efficiency compared to conventional single-gate (SG) transistors and is expected to enhance the overall performance of A-CNT transistors.

Sub-180-nanometer-thick ultraconformable high-performance carbon nanotube-based dual-gate transistors and differential amplifiers.

There is increased interest in ultrathin flexible devices with thicknesses of <1 micrometers due to excellent conformability toward advanced laminated bioelectronics. However, because of limitations in materials, device structure, and fabrication methodology, the performance of these ultrathin devices and circuits is insufficient to support higher-level applications. Here, we report high-performance carbon nanotube-based thin-film transistors (TFTs) and differential amplifiers on ultrathin polyimide films with a total thickness of <180 nanometers.

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data.

Aligned carbon nanotube-based electronics on glass wafer.

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority.

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping.

Diodes based on p-n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form p- or n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness.

Improving Carbon Nanotube-Based Radiofrequency Field-Effect Transistors by the Device Architecture and Doping Process.

The semiconducting carbon nanotube (CNT) has been considered a promising candidate for future radiofrequency (RF) electronics due to its excellent electrical properties of high mobility and small capacitance. After decades of development, great progress has been achieved on CNT-based RF field-effect transistors (FETs). However, almost all elevations are owing to advancement of the CNT materials and fabrication process, while the study of device architecture is seldom considered and reported.

Unzipping Carbon Nanotubes to Sub-5-nm Graphene Nanoribbons on Cu(111) by Surface Catalysis.

Graphene nanoribbons (GNRs) are promising in nanoelectronics for their quasi-1D structures with tunable bandgaps. The methods for controllable fabrication of high-quality GNRs are still limited. Here a way to generate sub-5-nm GNRs by annealing single-walled carbon nanotubes (SWCNTs) on Cu(111) is demonstrated.