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Article Abstract
A novel low-power delay time cancellation (LPDTC) technique and a current ratio adjustment (CRA) method are proposed for designing high-precision relaxation oscillators. These methods effectively reduce the impacts of comparator delay time, offset voltage, and temperature-induced variations in resistors. To validate these methods, we have designed and simulated an 8 MHz open-loop relaxation oscillator using a 40 nm CMOS process. The oscillator, incorporating these advanced methods, achieves a line sensitivity of 0.38%/V and a temperature sensitivity of 43 ppm/°C over a temperature range of -40 °C to 125 °C.
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| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC12029607 | PMC |
| http://dx.doi.org/10.3390/mi16040364 | DOI Listing |
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