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An enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron- mobility-transistor was fabricated using a recess gate and CF plasma treatment to investigate its reliable applicability to high-power devices and circuits. The fluorinated-gate device showed hysteresis during the DC current-voltage measurement, and the polarity and magnitude of hysteresis depend on the drain voltage. The hysteresis phenomenon is due to the electron trapping at the AlO/AlGaN interface and charging times longer than milliseconds were obtained by pulse I-V measurement. In addition, the subthreshold slope of the fluorinated-gate device was increased after the positive gate bias stress because of the two-dimensional electron gas reduction by ionized fluorine. Our systematic observation revealed that the effect of fluorine ions should be considered for the design of AlGaN/GaN power circuits.
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http://dx.doi.org/10.3390/nano10112116 | DOI Listing |
Micromachines (Basel)
February 2025
School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400030, China.
In this article, a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD) is proposed and analyzed through TCAD simulations. The MCD incorporates a short channel, where the channel length can be adjusted by modifying the recess depth. Owing to the drain-induced barrier-lowering (DIBL) effect, a low potential barrier is created for electrons flowing from the JFET region to the N+ source region.
View Article and Find Full Text PDFNanomaterials (Basel)
June 2024
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea.
The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor ()-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.
View Article and Find Full Text PDFMicromachines (Basel)
August 2023
Department of Photonics, Institute of Electro-Optical Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
A typical method for normally-off operation, the metal-insulator-semiconductor-high electron mobility transistor (MIS-HEMT) has been investigated. Among various approaches, gate recessed MIS-HEMT have demonstrated a high gate voltage sweep and low leakage current characteristics. Despite their high performance, obtaining low-damage techniques in gate recess processing has so far proven too challenging.
View Article and Find Full Text PDFMicromachines (Basel)
May 2023
School of Microelectronics, Fudan University, Shanghai 200433, China.
In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial SiGe layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations.
View Article and Find Full Text PDFNanomaterials (Basel)
September 2022
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Gyeongbuk, Korea.
The inner spacer thickness (T) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T variation (ΔT). The gate length (L) depends on the T.
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