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Article Abstract
In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 [Formula: see text]m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via [Formula: see text]-well. The metal wires of [Formula: see text] use [Formula: see text] substrate to contact [Formula: see text], to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.
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| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC12340108 | PMC |
| http://dx.doi.org/10.1038/s41598-025-14874-4 | DOI Listing |
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