Material-Specific Diffusion Barrier Performance of AlO for p-Type and n-Type Oxide Semiconductors in Oxide-Based CMOS Applications.

A p-type oxide semiconductor can advance oxide electronics by enabling bipolar applications, such as p-n junctions and complementary logic devices. As a single-cation species, p-type SnO (p-SnO) offers processing simplicity, easier manipulation of doping and other properties, and reduced carrier scattering, which is favorable for carrier transport compared to multication or complex p-type oxides. However, the mono-oxide phase, SnO (p-type), is thermodynamically unstable and tends to oxidize further to form the dioxide phase, SnO (n-type). Additionally, hydrogen, the lightest and smallest element present in air, can be incorporated into p-SnO and modulate its doping level. To mitigate these instabilities and ensure the reliable performance of p-SnO, a functional barrier layer is required to limit the diffusion of elements like oxygen and hydrogen into the p-SnO. AlO is selected as a thin encapsulation layer due to its well-known gas diffusion barrier properties, and the p-SnO properties, specifically with AlO, are comprehensively investigated. Density functional theory and molecular dynamics calculations suggest significantly lower adsorption, dissociation, and migration events involving hydrogen in the AlO/p-SnO bilayer compared to nonbarriered p-SnO. These theoretical studies are validated through a series of experimental investigations, including time-of-flight secondary ion mass spectrometry depth profiling and microstructure/composition analysis. For practical applications, the developed and encapsulated p-SnO is employed in a bipolar application of complementary logic devices with n-type InZnO (IZO), and its performance is compared to unencapsulated counterparts. Air annealing at 300 °C for 4 h stabilizes both p-type SnO and n-type IZO, resulting in devices with excellent uniformity and less than ±6% variation in key performance metrics. Encapsulated complementary devices demonstrate significantly enhanced logic inverter performance with a high gain of 170 V/V, compared to 29 V/V for unencapsulated devices. This enhanced performance is attributed to the suppressed carrier density and surface defects in oxide channels due to the limited diffusion of H and O, leading to favorable threshold voltage matches and enhanced carrier transport.