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Gate-all-around (GAA) nanosheet field-effect transistors (FETs) have significantly advanced nanoscale device technology by mitigating short-channel effects. These GAA structures are becoming essential in sub-3 nm technology and are evolving into complementary FETs. Despite the reduction in variability achieved by multi-gate structures, random discrete dopants (RDDs) in source and drain (S/D) regions continue to pose challenges. This study addresses the local variability induced by RDDs, particularly in the S/D extensions in GAA nanosheet FETs. Through statistical quantum transport simulations under a ballistic approximation, we investigate parameters such as spacer length, channel width, and channel thickness. The results show that RDDs in the S/D extensions cause not only threshold voltage variation but also increase resistance and reduce ON-state current. GAA nanosheet FETs with a3 nm×10 nmcross-sectional channel and 5 nm spacer length exhibit 10% reduction in ON-state current compared to the ideal device, along with a standard deviation (variability) of 0.35A. Mitigation of these effects requires the use of thin, wide, and large cross-section nanosheets and short spacer lengths.
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http://dx.doi.org/10.1088/1361-6528/adc606 | DOI Listing |
Small
September 2025
Department of System Semiconductor Engineering and Department of Materials Science and Engineering, Yonsei University, Seoul, 03722, South Korea.
2D materials have emerged as promising candidates for next-generation field-effect transistors (FETs) owing to the atomically thin geometry and excellent electrostatic gate control. Here, double-gate vertical sidewall FETs based on chemical vapor deposition-grown monolayer WS are demonstrated and, for the first time, report vertical multi-channel nanosheet FETs (NSFETs). By implementing a dual-step sidewall profile, steep SiO surfaces are obtained, which enabled seamless WS adhesion and contributed to enhanced device yield.
View Article and Find Full Text PDFACS Nano
June 2025
Engineering Science and Mechanics, Penn State University, University Park 16802, United States.
Development and integration of gate insulators that offer a low equivalent oxide thickness (EOT) while maintaining a physically thicker layer are critical for advancing transistor technology as device dimensions continue to shrink. Such materials can deliver high gate capacitance and yet reduce gate leakage, thereby minimizing static power dissipation without compromising performance. These insulators should also provide the necessary interface quality, thermal stability, switching endurance, and reliability.
View Article and Find Full Text PDFNanotechnology
April 2025
James Watt School of Engineering, University of Glasgow, Glasgow, Scotland, United Kingdom.
Gate-all-around (GAA) nanosheet field-effect transistors (FETs) have significantly advanced nanoscale device technology by mitigating short-channel effects. These GAA structures are becoming essential in sub-3 nm technology and are evolving into complementary FETs. Despite the reduction in variability achieved by multi-gate structures, random discrete dopants (RDDs) in source and drain (S/D) regions continue to pose challenges.
View Article and Find Full Text PDFAdv Sci (Weinh)
May 2025
Department of Electrical Engineering, Hanyang University, Seoul, 04763, Republic of Korea.
A material design method is proposed using ferroelectric (FE)-antiferroelectric (AFE) mixed-phase HfZrO (HZO) to achieve performance improvements in morphotropic phase boundary (MPB) field-effect transistors (MPB-FETs), such as steep subthreshold swing (SS) and non-hysteretic on-current (I) enhancement. Capacitance (small-signal and quasi-static) and transient current measurements of MPB-FETs confirmed that near-threshold voltage (V) capacitance amplification leads to I boosts under high-speed and low-power conditions. For the first time, two-stacked nanosheet (NS) gate-all-around (GAA) MPB-FETs with optimized HZO, demonstrating superior short channel effect (SCE) immunity with enhanced current drivability is fabricated.
View Article and Find Full Text PDFNat Commun
March 2025
School of Physics, State Key Laboratory of Powder Metallurgy, Hunan Key Laboratory of Nanophotonics and Devices, Central South University, Changsha, Hunan, China.
The experimental realization of single-crystalline high-κ dielectrics beyond two-dimensional (2D) layered materials is highly desirable for nanoscale field-effect transistors (FETs). However, the scalable synthesis of 2D nonlayered high-κ insulators is currently limited by uncontrolled isotropic three-dimensional growth, hampering the achievement of simultaneous high dielectric constants and low trap densities for small film thicknesses. Herein, we show a 2D edge-seeded heteroepitaxial strategy to synthesize ultrathin nonlayered 2D CaNbO nanosheets by chemical vapor deposition, exhibiting high-crystalline quality, thickness-independent dielectric constant (~ 16) and breakdown field strength up to ~ 12 MV cm.
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