98%
921
2 minutes
20
Amorphous IGZO (a-IGZO) thin-film transistors (TFTs) are standard backplane electronics to power active-matrix organic light-emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid-size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma-enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the MO (M = In or Ga) surface layer, partial conversion of the underlying MO to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In-Ga-Zn (Case I) and In-Zn-Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a-IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313 mV decade) and high mobility (µ) of 29.3 cm2 Vs (Case I: 84 mV decade and 33.4 cm Vs). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In-Zn defects, supported by technology computer-aided design (TCAD) simulations.
Download full-text PDF |
Source |
---|---|
http://dx.doi.org/10.1002/smtd.202301185 | DOI Listing |
Adv Mater
September 2025
State Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, 100029, China.
The monolayer transistor, where the semiconductor layer is a single molecular layer, offers an ideal platform for exploring transport mechanisms both theoretically and experimentally by eliminating the influence of spatially correlated microstructure. However, the structure-property relations in polymer monolayers remain poorly understood, leading to low transistor performance to date. Herein, a self-confinement effect is demonstrated in the polymer monolayer with nanofibrillar microstructures and edge-on orientation, as characterized by the 4D scanning confocal electron diffraction method.
View Article and Find Full Text PDFACS Nano
September 2025
Department of Chemical Engineering, Stanford University, Stanford, California 94305, United States.
Integration of ultrathin, high-quality gate insulators is critical to the success of two-dimensional (2D) semiconductor transistors in next-generation nanoelectronics. Here, we investigate the impact of atomic layer deposition (ALD) precursor choice on the nucleation and growth of insulators on monolayer MoS. Surveying a series of aluminum (AlO) precursors, we observe that increasing the length of the ligands reduces the nucleation delay of alumina on monolayer MoS, a phenomenon that we attribute to improved van der Waals dispersion interactions with the 2D material.
View Article and Find Full Text PDFAdv Mater
September 2025
Department of Advanced Materials Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-Gu, Cheongju, Chungbuk, 28644, Republic of Korea.
In this study, the first sub-60 mV dec super-steep subthreshold swing (SS) of graphene/InGaZnO (IGZO) cold-source field-effect transistor (CSFET) arrays is demonstrated. The linear density of states of the Dirac-cone-type graphene suppresses the Boltzmann thermal tail near the graphene/IGZO interface which in turn causes super-exponentially decaying electron density with increasing energy, leading to an extremely low off current and SS value. In particular, by introducing an HfO high-k dielectric with a low body factor, the surface potential is effectively modulated, further reducing SS by ≈46.
View Article and Find Full Text PDFSmall
September 2025
Department of System Semiconductor Engineering and Department of Materials Science and Engineering, Yonsei University, Seoul, 03722, South Korea.
2D materials have emerged as promising candidates for next-generation field-effect transistors (FETs) owing to the atomically thin geometry and excellent electrostatic gate control. Here, double-gate vertical sidewall FETs based on chemical vapor deposition-grown monolayer WS are demonstrated and, for the first time, report vertical multi-channel nanosheet FETs (NSFETs). By implementing a dual-step sidewall profile, steep SiO surfaces are obtained, which enabled seamless WS adhesion and contributed to enhanced device yield.
View Article and Find Full Text PDFMicromachines (Basel)
July 2025
Key Laboratory of Wide Bandgap Semiconductor Materials, Faculty of Integrated Circuit, Ministry of Education, Xidian University, Xi'an 710071, China.
The development of an integrated circuit faces the challenge of the physical limit of Moore's Law. One of the most important "Beyond Moore" challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down.
View Article and Find Full Text PDF