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Progress in artificial intelligence (AI) demands efficient data storage and high-speed processing. Traditional von Neumann architecture, with space separation of memory and computing units, struggles with increased data transmission, causing power inefficiency and date latency. To address this challenge, we designed a semi-floating gate transistor (SFGT) that integrates data storage and logical operation into a single device by employing a ferroelectric semiconductor α-InSe as a semi-floating gate layer. Leveraging the ferroelectric polarization of α-InSe, the device exhibits improved non-volatile memory performance with a high program/erase ratio of 1 × 10 and reliable durability over 1000 cycles. Through the dual-gate modulation, the SFGT achieves multilevel storage function with at least seven controllable programming states and performs three types of digital logic gate operations ("AND", "NOR", and "OR") at an ultralow bias of 10 mV. Compared to traditional FGT architectures, the α-InSe-based semi-floating gate structure achieves multifunctional integration of data storage and logic computing, effectively addressing energy consumption and time delay issues in data transmission, making it highly significant for applications in data-intensive and low-power integrated circuits.
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http://dx.doi.org/10.1021/acsami.5c01586 | DOI Listing |
Two-dimensional (2D) material photodetector based on semi-floating gate (SFG) structure is expected to achieve multiple functions of information sensing, storage, and processing in a single device. Here, we demonstrated a terahertz (THz) detector based on the graphene/h-BN/graphene SFG structure. The device exhibits an excellent memory behavior and a gate-controlled non-volatile and multistate photothermoelectric (PTE) THz response.
View Article and Find Full Text PDFACS Appl Mater Interfaces
May 2025
Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
Progress in artificial intelligence (AI) demands efficient data storage and high-speed processing. Traditional von Neumann architecture, with space separation of memory and computing units, struggles with increased data transmission, causing power inefficiency and date latency. To address this challenge, we designed a semi-floating gate transistor (SFGT) that integrates data storage and logical operation into a single device by employing a ferroelectric semiconductor α-InSe as a semi-floating gate layer.
View Article and Find Full Text PDFAdv Sci (Weinh)
June 2025
Engineering Research Center of IoT Technology Applications (Ministry of Education) School of Integrated Circuits, Jiangnan University, Wuxi, 214122, China.
Programmable photovoltaic photodetectors based on 2D materials can modulate optical and electronic signals in parallel, making them particularly well-suited for optoelectronic hybrid dual-channel communication. This work presents a programmable non-volatile bipolar semi-floating gate photovoltaic photodetector (SFG-PD) constructed using tungsten diselenide (WSe), hexagonal boron nitride (h-BN), and graphene (Gra). By controlling the voltage pulses applied to the control gate, the device generates opposing built-in electric field junctions (p-p and n-p junctions), enabling reversible switching between positive and negative light responses with a rapid response time of up to 2.
View Article and Find Full Text PDFNat Commun
July 2024
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, 200433, China.
Nanotechnology
October 2023
College of Optical and Electronic Technology, China Jiliang University, Hangzhou 310013, People's Republic of China.
Semi-floating gate transistors based on vdW materials are often used in memory and programmable logic applications. In this paper, we propose a semi-floating gate photoelectric p-n junction transistor structure which is stacked by InSe/h-BN/Gr. By modulating gate voltage, InSe can be presented as N-type and P-type respectively on different substrates, and then combined into p-n junction.
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