Enhanced Synaptic Memory Window and Linearity in Planar InSe Ferroelectric Junctions.

A synaptic memristor using 2D ferroelectric junctions is a promising candidate for future neuromorphic computing with ultra-low power consumption, parallel computing, and adaptive scalable computing technologies. However, its utilization is restricted due to the limited operational voltage memory window and low on/off current (I) ratio of the memristor devices. Here, it is demonstrated that synaptic operations of 2D InSe ferroelectric junctions in a planar memristor architecture can reach a voltage memory window as high as 16 V (±8 V) and I ratio of 10, significantly higher than the current literature values. The power consumption is 10 W at the on state, demonstrating low power usage while maintaining a large I ratio of 10 compared to other ferroelectric devices. Moreover, the developed ferroelectric junction mimicked synaptic plasticity through pulses in the pre-synapse. The nonlinearity factors are obtained 1.25 for LTP, -0.25 for LTD, respectively. The single-layer perceptron (SLP) and convolutional neural network (CNN) on-chip training results in an accuracy of up to 90%, compared to the 91% in an ideal synapse device. Furthermore, the incorporation of a 3 nm thick SiO interface between the α-InSe and the Au electrode resulted in ultrahigh performance among other 2D ferroelectric junction devices to date.