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Recently, we reported that device performance degradation mechanisms, which are generated by the γ-ray irradiation in GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs), use extremely thin gate insulators. When the γ-ray was radiated, the total ionizing dose (TID) effects were generated and the device performance deteriorated. In this work, we investigated the device property alteration and its mechanisms, which were caused by the proton irradiation in GaN-based MIS-HEMTs for the 5 nm-thick SiN and HfO gate insulator. The device property, such as threshold voltage, drain current, and transconductance varied by the proton irradiation. When the 5 nm-thick HfO layer was employed for the gate insulator, the threshold voltage shift was larger than that of the 5 nm-thick SiN gate insulator, despite the HfO gate insulator exhibiting better radiation resistance compared to the SiN gate insulator. On the other hand, the drain current and transconductance degradation were less for the 5 nm-thick HfO gate insulator. Unlike the γ-ray irradiation, our systematic research included pulse-mode stress measurements and carrier mobility extraction and revealed that the TID and displacement damage (DD) effects were simultaneously generated by the proton irradiation in GaN-based MIS-HEMTs. The degree of the device property alteration was determined by the competition or superposition of the TID and DD effects for the threshold voltage shift and drain current and transconductance deterioration, respectively. The device property alteration was diminished due to the reduction of the linear energy transfer with increasing irradiated proton energy. We also studied the frequency performance degradation that corresponded to the irradiated proton energy in GaN-based MIS-HEMTs using an extremely thin gate insulator.
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http://dx.doi.org/10.3390/nano13050898 | DOI Listing |
ACS Nano
September 2025
Department of Chemical Engineering, Stanford University, Stanford, California 94305, United States.
Integration of ultrathin, high-quality gate insulators is critical to the success of two-dimensional (2D) semiconductor transistors in next-generation nanoelectronics. Here, we investigate the impact of atomic layer deposition (ALD) precursor choice on the nucleation and growth of insulators on monolayer MoS. Surveying a series of aluminum (AlO) precursors, we observe that increasing the length of the ligands reduces the nucleation delay of alumina on monolayer MoS, a phenomenon that we attribute to improved van der Waals dispersion interactions with the 2D material.
View Article and Find Full Text PDFACS Appl Mater Interfaces
September 2025
Department of Material Sciences and Engineering, Seoul National University, Seoul 08826, Republic of Korea.
A nanometer-scale multilayer gate insulator (GI) engineering strategy is introduced to simultaneously enhance the on-current and bias stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Atomic layer deposition supercycle modifications employ alternating layers of AlO, TiO, and SiO to optimize the gate-oxide stack. Each GI material is strategically selected for complementary functionalities: AlO improves the interfacial quality at both the GI/semiconductor and GI/metal interfaces, thereby enhancing device stability and performance; TiO increases the overall dielectric constant; and SiO suppresses leakage current by serving as a high-energy barrier between AlO and TiO.
View Article and Find Full Text PDFNat Commun
August 2025
Key Laboratory for the Physics and Chemistry of Nanodevices, School of Electronics, Peking University, Beijing, China.
Hexagonal boron nitride (hBN) nanosheets have become the most promising candidates as gate dielectric and insulating substrates for two-dimensional (2D) material-based electronic and optoelectronic devices. While mechanical stress in hBN nanosheets is often either intrinsically or intentionally introduced for 2D material-based devices during device fabrication and operation, the dielectric strength of hBN nanosheets under mechanical stress is still elusive. In this work, the dielectric strength of hBN nanosheets in a metal/hBN/metal structure is systematically studied when mechanical stress normal to nanosheets is applied.
View Article and Find Full Text PDFMicromachines (Basel)
July 2025
Faculty of Technology, School of Electrical and Mechanical Engineering, University of Portsmouth, Portsmouth PO1 3DJ, UK.
As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S-FinFET) that incorporates a three-layer HfO/SiN/HfO spacer configuration designed to enhance electrostatics and suppress parasitic effects.
View Article and Find Full Text PDFWe present the first, to the best of our knowledge, passive on-chip Boolean NOT gate using a phase-only waveguide Bragg grating (WBG) on a silicon-on-insulator platform. The spiral geometry enables a compact 0.25-mm footprint while achieving inversion of 50-Gbps PAM-2 and 45-Gbps PAM-3 signals without active or nonlinear components.
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