Enhancement of On-Current and Reliability in InGaZnO Thin-Film Transistors for Synaptic Circuit Applications through Gate Insulator Stack Engineering.

A nanometer-scale multilayer gate insulator (GI) engineering strategy is introduced to simultaneously enhance the on-current and bias stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Atomic layer deposition supercycle modifications employ alternating layers of AlO, TiO, and SiO to optimize the gate-oxide stack. Each GI material is strategically selected for complementary functionalities: AlO improves the interfacial quality at both the GI/semiconductor and GI/metal interfaces, thereby enhancing device stability and performance; TiO increases the overall dielectric constant; and SiO suppresses leakage current by serving as a high-energy barrier between AlO and TiO.

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy.