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The metal-type microbolometers in CMOS technology normally suffer low resistivity and high thermal conductivity, limiting their performance and application areas. In this paper, we demonstrate a polysilicon microbolometer fabricated in 0.18 µm CMOS and post-CMOS processes. The detector is composed of a SiO absorber coupled with a salicided poly-Si thermistor that has a high resistivity of 1.37×10 Ω·cm and low thermal conductivity of 18 W/m·K. It is experimentally shown that the microbolometer with a 40 µm × 40 µm pixel size has a maximum responsibility and detectivity of 2.13×10 V/W and 2.33×10 cmHz/W, respectively. The results are superior to the reported metal-type and diode-type microbolometers in the CMOS process and provide good potential for a low-cost, high-performance, uncooled microbolometer array for infrared imaging applications.
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http://dx.doi.org/10.1364/OE.439970 | DOI Listing |
Adv Mater
September 2025
State Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, 100029, China.
The monolayer transistor, where the semiconductor layer is a single molecular layer, offers an ideal platform for exploring transport mechanisms both theoretically and experimentally by eliminating the influence of spatially correlated microstructure. However, the structure-property relations in polymer monolayers remain poorly understood, leading to low transistor performance to date. Herein, a self-confinement effect is demonstrated in the polymer monolayer with nanofibrillar microstructures and edge-on orientation, as characterized by the 4D scanning confocal electron diffraction method.
View Article and Find Full Text PDFBiosens Bioelectron
September 2025
Microtechnology for Neuroelectronics Unit (NetS(3) lab), Fondazione Istituto Italiano di Tecnologia, Genova, Italy.
Achieving stable and continuous monitoring of signals of numerous single neurons in the brain faces the conflicting challenge of increasing the microelectrode count while minimizing cross-sectional shank dimensions to reduce tissue damage, foreign-body-reaction and maintain signal quality. Passive probes need to route each microelectrode individually to external electronics, thus increasing shank size and tissue-damage as the number of electrodes grows. Active complementary metal-oxide-semiconductor (CMOS) probes overcome the limitation in electrode count and density with on-probe frontend, addressing and multiplexing circuits, but current probes have relatively large shank widths of 70 - 100 μm.
View Article and Find Full Text PDFACS Appl Mater Interfaces
September 2025
Nanoelectronics Graphene and 2D Materials Laboratory, CITIC-UGR, Department of Electronics, University of Granada, Granada 18014, Spain.
The relentless scaling of semiconductor technology demands materials beyond silicon to sustain performance improvements. Transition metal dichalcogenides (TMDs), particularly MoS, offer excellent electronic properties; however, achieving scalable and CMOS-compatible fabrication remains a critical challenge. Here, we demonstrate a scalable and BEOL-compatible approach for the direct wafer-scale growth of MoS devices using plasma-enhanced atomic layer deposition (PE-ALD) at temperatures below 450 °C, fully compliant with CMOS thermal budgets.
View Article and Find Full Text PDFFront Neurosci
August 2025
Department of Electronics, Graduate School of Engineering, Tohoku Institute of Technology, Sendai, Japan.
Introduction: Human iPSC-derived brain organoids and assembloids have emerged as promising in vitro models for recapitulating human brain development, neurological disorders, and drug responses. However, detailed analysis of their electrophysiological properties requires advanced measurement techniques.
Methods: Here, we present an analytical approach using ultra-high-density (UHD) CMOS microelectrode arrays (MEAs) with 236,880 electrodes across a 32.
Nano Lett
September 2025
Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States of America.
Wurtzite nitride ferroelectric materials have emerged as promising candidates for next-generation memory applications, due to their exceptional polarization properties and compatibility with conventional semiconductor processing techniques. Here, we demonstrate the first successful areal scaling of aluminum scandium nitride (AlScN) ferroelectric diode (FeDiode) memory down to device diameter of 40 nm while maintaining an ON/OFF ratio of >60. Using a 20-nm-thick AlScN ferroelectric layer, we evaluate both metal-insulator-ferroelectric-metal (MIFM) and metal-ferroelectric-metal (MFM) architectures for scaled resistive memory devices.
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