Synergistic Breakthrough in Speed and Power: TiO/SiO Stacked Dielectric Heterostructures for Phase-Change Memory.

Phase-change memory (PCM) emerges as a leading contender for storage-class memory applications yet faces inherent trade-offs between SET speed and RESET power due to competing crystallization and melt-quench dynamics. Herein, we demonstrate a stacked dielectric heterostructure strategy integrating lattice-matched TiO and thermal-confining SiO interlayers to overcome these limitations. The crystalline TiO layer lowers nucleation barriers via epitaxial matching, while the ultralow thermal conductivity SiO layer confines Joule heating localization via thermal-field regulation. By optimizing interlayer thicknesses guided by Poole-Frenkel emission modeling and interface state density analysis, the stacked dielectric PCM device achieves synchronized breakthroughs: 8 ns ultrafast speed (meeting DRAM-grade speed) and 2 pJ ultralow energy consumption. Finally, the localized thermal confinement capability of SiO induced by Joule heating and the crystallographic plane matching of TiO have been corroborated through finite element simulations and TEM characterization. This work further advances the development of PCM for high-speed cache memory applications.