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In this study, we propose an optimized shield gate trench 4H-SiC structure with effective gate oxide protection. The proposed device has a split trench with a P+ shield region, and the P+ shield is grounded by the middle deep trench. Our simulation results show that the peak electric field near the gate oxide is almost completely suppressed. Compared with a conventional P+ shield device, our proposed structure achieves a 78% reduction in the Q and a 108% increase in the FoM (figure of merit) simultaneously. Additionally, it is estimated that the device cell pitch can be reduced to 1.8 μm with a R below 0.94 mΩ·cm, in theory. These demonstrated device performance metrics, as well as its simple structure and good compatibility, make our proposed SiC MOSFET highly attractive for future high-performance applications.
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http://dx.doi.org/10.3390/mi16040447 | DOI Listing |
ACS Appl Mater Interfaces
September 2025
National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan.
In this study, we analyze InO thin-film transistors (InO-TFT) using synchrotron-based hard X-ray photoelectron spectroscopy (HAXPES) in conditions. A bottom-gate InO-TFT with a high- AlO gate dielectric, grown on thermally oxidized silicon (SiO/p-Si), was examined while operating at varying and . The results reveal that the In 3d core level binding energy varies along the horizontal channel length, driven by the potential gradient induced by .
View Article and Find Full Text PDFAdv Mater
September 2025
State Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, 100029, China.
The monolayer transistor, where the semiconductor layer is a single molecular layer, offers an ideal platform for exploring transport mechanisms both theoretically and experimentally by eliminating the influence of spatially correlated microstructure. However, the structure-property relations in polymer monolayers remain poorly understood, leading to low transistor performance to date. Herein, a self-confinement effect is demonstrated in the polymer monolayer with nanofibrillar microstructures and edge-on orientation, as characterized by the 4D scanning confocal electron diffraction method.
View Article and Find Full Text PDFACS Nano
September 2025
School of Microelectronics, University of Science and Technology of China, Hefei, Anhui 230026, China.
Superlinear photodetectors hold significant potential in intelligent optical detection systems, such as near-field imaging. However, their current realization imposes stringent requirements on photosensitive materials, thereby limiting the flexibility of the device integration for practical applications. Herein, a tunable superlinear GaO deep-ultraviolet gate-all-around (GAA) phototransistor based on a p-n heterojunction has been proposed.
View Article and Find Full Text PDFACS Nano
September 2025
Department of Chemical Engineering, Stanford University, Stanford, California 94305, United States.
Integration of ultrathin, high-quality gate insulators is critical to the success of two-dimensional (2D) semiconductor transistors in next-generation nanoelectronics. Here, we investigate the impact of atomic layer deposition (ALD) precursor choice on the nucleation and growth of insulators on monolayer MoS. Surveying a series of aluminum (AlO) precursors, we observe that increasing the length of the ligands reduces the nucleation delay of alumina on monolayer MoS, a phenomenon that we attribute to improved van der Waals dispersion interactions with the 2D material.
View Article and Find Full Text PDFACS Appl Mater Interfaces
September 2025
Department of Material Sciences and Engineering, Seoul National University, Seoul 08826, Republic of Korea.
A nanometer-scale multilayer gate insulator (GI) engineering strategy is introduced to simultaneously enhance the on-current and bias stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Atomic layer deposition supercycle modifications employ alternating layers of AlO, TiO, and SiO to optimize the gate-oxide stack. Each GI material is strategically selected for complementary functionalities: AlO improves the interfacial quality at both the GI/semiconductor and GI/metal interfaces, thereby enhancing device stability and performance; TiO increases the overall dielectric constant; and SiO suppresses leakage current by serving as a high-energy barrier between AlO and TiO.
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