Category Ranking
98%
Total Visits
921
Avg Visit Duration
2 minutes
Citations
20
Article Abstract
The emerging demand of data storage in wearable devices, flexible circuits based on organic semiconductor materials are encouraged, while organic field effect transistors face the challenges of low operating voltage and high on/off ratio. In this work, a high-performance flexible organic field effect transistor (OFET) is built with a threshold voltage range of -0.45 to -0.86 V and an on/off ratio between 10 and 10. The subthreshold swing of the OFETs is lower than 60 mV dec. Through finite element analysis, the OFET shows excellent mechanical stability owing to the stress relief during the bending process. Furthermore, a flexible 2T0C DRAM cell is demonstrated based on the OFETs. The stable electrical characteristics of the OFETs enable the 2T0C DRAM cell to achieve a retention time exceeding 300 s under both initial and bending conditions. Additionally, 2-bit memory operations are realized by adjusting the voltage of the word bit line (V) and the voltage of the word write line (V), demonstrating consistent performance in both the initial and after-bending state.
Download full-text PDF |
Source |
|---|---|
| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC12061271 | PMC |
| http://dx.doi.org/10.1002/advs.202500300 | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
Retention and endurance analysis for 2T0C DRAM based on ALD-ITZO thin film transistors.
Nanotechnology
June 2025
Fudan University, Handan Road 220, Yangpu Disctrict, Shanghai, Shanghai, Shanghai, 200433, CHINA.
DRAM technology is crucial in modern integrated circuits. However, the conventional 1T1C DRAM is approaching its limitations in scalability near 10 nm technical node, posing challenges for storage capacity and integration. Therefore, research has focused on incorporating 3D-stacking DRAM to enhance both capacity and integration.
View Article and Find Full Text PDF3D stacked IGZO 2T0C DRAM array with multibit capability for computing in memory applications.
Sci Adv
May 2025
School of Integrated Circuits and Wuhan National High Magnetic Field Center, Huazhong University of Science and Technology, Wuhan 430074, China.
Traditional dynamic random access memory (DRAM) technology faces grand challenges in power consumption due to the constant data refresh and in density due to the physical limit for dimension scaling. Recently, two-transistor zero-capacitor (2T0C) DRAM based on amorphous indium gallium zinc oxide (IGZO) exhibits long data retention owing to its extremely low off-state leakage current. Furthermore, the low thermal budget of the IGZO channel enables the monolithic three-dimensional (3D) stacking for higher bit density beyond the planar scaling limit.
View Article and Find Full Text PDFFlexible Organic Field-Effect Transistor (OFET) Based 2T0C DRAM Cells with 2-Bit Operation and Extended Retention.
Adv Sci (Weinh)
May 2025
School of Microelectronics, State Key Laboratory of Integrated Chip and System, Fudan University, Shanghai, 200433, P. R. China.
The emerging demand of data storage in wearable devices, flexible circuits based on organic semiconductor materials are encouraged, while organic field effect transistors face the challenges of low operating voltage and high on/off ratio. In this work, a high-performance flexible organic field effect transistor (OFET) is built with a threshold voltage range of -0.45 to -0.
View Article and Find Full Text PDFITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM.
ACS Omega
January 2025
School of Integrated Technology, Yonsei University, Seoul 03722, Republic of Korea.
We developed a two-transistor, zero-capacitor (2T0C) gain-cell memory featuring a self-aligned top-gate-structured thin-film transistor (TFT) for the first time. The proposed indium tin zinc oxide (ITZO) channel-incorporated architecture was specifically engineered to minimize parasitic capacitance for achieving long-retention 2T0C memory operations. A typical 2T0C structure features five types of parasitic capacitances; however, the proposed SATG design effectively used an essential gate insulator capacitance ( ) and reduced four nonessential capacitances ( , , , and ) to virtually zero.
View Article and Find Full Text PDFCapacitorless Dynamic Random Access Memory with 2D Transistors by One-Step Transfer of van der Waals Dielectrics and Electrodes.
ACS Nano
January 2025
Department of Applied Physics, The Hong Kong Polytechnic University, Kowloon, Hong Kong 999077, China.
Dynamic random access memory (DRAM) has been a cornerstone of modern computing, but it faces challenges as technology scales down, particularly due to the mismatch between reduced storage capacitance and increasing OFF current. The capacitorless 2T0C DRAM architecture is recognized for its potential to offer superior area efficiency and reduced refresh rate requirements by eliminating the traditional capacitor. The exploration of two-dimensional (2D) materials further enhances scaling possibilities, though the absence of dangling bonds complicates the deposition of high-quality dielectrics.
View Article and Find Full Text PDF