Severity: Warning
Message: file_get_contents(https://...@gmail.com&api_key=61f08fa0b96a73de8c900d749fcb997acc09&a=1): Failed to open stream: HTTP request failed! HTTP/1.1 429 Too Many Requests
Filename: helpers/my_audit_helper.php
Line Number: 197
Backtrace:
File: /var/www/html/application/helpers/my_audit_helper.php
Line: 197
Function: file_get_contents
File: /var/www/html/application/helpers/my_audit_helper.php
Line: 271
Function: simplexml_load_file_from_url
File: /var/www/html/application/helpers/my_audit_helper.php
Line: 3165
Function: getPubMedXML
File: /var/www/html/application/controllers/Detail.php
Line: 597
Function: pubMedSearch_Global
File: /var/www/html/application/controllers/Detail.php
Line: 511
Function: pubMedGetRelatedKeyword
File: /var/www/html/index.php
Line: 317
Function: require_once
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A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (E) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that E depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.
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http://dx.doi.org/10.1002/adma.202314274 | DOI Listing |