IEEE J Biomed Health Inform
June 2020
Objective: Cardiovascular Implantable Electronic Devices (CIEDs) are used extensively for treating life-threatening conditions such as bradycardia, atrioventricular block and heart failure. The complicated heterogeneous physical dynamics of patients provide distinct challenges to device development and validation. We address this problem by proposing a device testing framework within the in-silico closed-loop context of patient physiology.
View Article and Find Full Text PDFOrgan level simulation of bioelectric behavior in the body benefits from flexible and efficient models of cellular membrane potential. These computational organ and cell models can be used to study the impact of pharmaceutical drugs, test hypotheses, assess risk and for closed-loop validation of medical devices. To move closer to the real-time requirements of this modeling a new flexible Fourier based general membrane potential model, called as a Resonant model, is developed that is computationally inexpensive.
View Article and Find Full Text PDFIEEE Trans Biomed Eng
February 2020
Objective: Evaluating and testing cardiac electrical devices in a closed-physiologic-loop can help design safety, but this is rarely practical or comprehensive. Furthermore, in silico closed-loop testing with biophysical computer models cannot meet the requirements of time-critical cardiac device systems, while simplified models meeting time-critical requirements may not have the necessary dynamic features. We propose a new high-level (abstracted) physiologically-based computational heart model that is time-critical and dynamic.
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January 2018
Objective: A flexible, efficient, and verifiable pacemaker cell model is essential to the design of real-time virtual hearts that can be used for closed-loop validation of cardiac devices. A new parametric model of pacemaker action potential is developed to address this need.
Methods: The action potential phases are modeled using hybrid automaton with one piecewise-linear continuous variable.
A new method for the parallel hardware implementation of artificial neural networks (ANNs) using digital techniques is presented. Signals are represented using uniformly weighted single-bit streams. Techniques for generating bit streams from analog or multibit inputs are also presented.
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