Radon reduction in small-scale water supply systems using low-technology reduction methods in the Republic of Korea: A field research and mass balance model approach.

In rural areas, low-technology radon reduction methods are essential for safe access to clean groundwater. This study monitored the radon reduction rates in small-scale groundwater-based water supply systems in the Republic of Korea and also presented a mass balance equation using physical environmental conditions from three radon reduction methods. The mass balance results showed that the radon reduction rate would be affected by the groundwater flow rate (m/day), capacity of the drainage facility (m), surface area of air-water interface (m), air-water ratio (dimensionless), and ventilation system.

A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory.

Resistive random-access memory (RRAM) is essential for developing neuromorphic devices, and it is still a competitive candidate for future memory devices. In this paper, a unified model is proposed to describe the entire electrical characteristics of RRAM devices, which exhibit two different resistive switching phenomena. To enhance the performance of the model by reflecting the physical properties such as the length index of the undoped area during the switching operation, the Voltage ThrEshold Adaptive Memristor (VTEAM) model and the tungsten-based model are combined to represent two different resistive switching phenomena.

New Simulation Method for Dependency of Device Degradation on Bending Direction and Channel Length.

The dependency of device degradation on bending direction and channel length is analyzed in terms of bandgap states in amorphous indium-gallium-zinc-oxide (a-IGZO) films. The strain distribution in an a-IGZO film under perpendicular and parallel bending of a device with various channel lengths is investigated by conducting a three-dimensional mechanical simulation. Based on the obtained strain distribution, new device simulation structures are suggested in which the active layer is defined as consisting of multiple regions.

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state.

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location.

Charge Based Current-Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor.

In this study, we propose an accurate and simple current-voltage model for an SOI-JLFET based on a solution of the Poisson equation. The model is divided into three regions: accumulation, accumulation-depletion, and depletion. The charge density in each region is calculated with the Poisson equation and region-specific boundary conditions, and then the current is obtained by integrating the charge density with consideration of the effect.

Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components.

A simplified OLED SPICE model with two resistors and two capacitors that have constant or voltagedependent (VD) values is proposed. Our model includes physical characteristics such as voltage and frequency dependency and agrees well with measurements. In this paper, we analyze the OLED frequency dependency effects and RC delay properties by controlling model parameters for DC, AC, and transient conditions.

Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses.

Amidst the considerable attention artificial intelligence (AI) has attracted in recent years, a neuromorphic chip that mimics the biological neuron has emerged as a promising technology. Memristor or Resistive random-access memory (RRAM) is widely used to implement a synaptic device. Recently, 3D vertical RRAM (VRRAM) has become a promising candidate to reducing resistive memory bit cost.

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking.

Memristor Neural Network Training with Clock Synchronous Neuromorphic System.

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with a memristor neural network. We showed that the nonlinear characteristic memristor neural network can be trained by unsupervised learning only with the correlation between inputs and outputs.

Analysis of the Memristor-Based Crossbar Synapse for Neuromorphic Systems.

In this study, we analyzed the memristor device typically used as a synapse in neuromorphic architecture and confirmed that the synaptic memristor device can be adopted to perform the machine learning algorithm. The nonlinear characteristics of the memristor complicates its use as the neuromorphic hardware in an artificial neural network (ANN) with a back-propagation algorithm. Using a memristor device with a nonlinear characteristic, we demonstrated that pattern classification can be implemented in ANNs using the Guide training algorithm without back-propagation.