Scalable Inter-Dielectric Engineering via Vapor-Phase Synthesis Process for Top-Gate MoS Thin-Film Transistor.

2D semiconductors are promising channel materials for next-generation thin-film transistors (TFTs) in Internet of Things (IoT) devices. However, their inert, dangling-bond-free surfaces make uniform high-k dielectric integration challenging and can lead to interface defect formation. Here, a scalable inter-dielectric engineering strategy is introduced to address this challenge, using initiated chemical vapor deposition (iCVD) to deposit an ultrathin nonpolar poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3) film as an interlayer between MoS and HfO. This pV3D3 buffer layer forms uniformly without pinholes or clusters on MoS, yielding excellent interface quality and effectively suppressing HfO-induced uncontrollable doping effect and trap formation in MoS. As a result, the MoS top-gate transistors with pV3D3/HfO dielectric exhibit nearly ideal switching characteristics, including a subthreshold swing (SS) of 60.9 mV dec, negligible hysteresis of ≈20 mV, and low interface trap density (D) of 8.9 × 10 cmeV. Furthermore, an overlapping top-gate structure design minimizes contact resistance, achieving an I/I ratio above 10, a field-effect mobility (µ) of 19.2 cmVs, and minimum subthreshold swing (SS) of 80.6 mV dec. This iCVD based inter-dielectric method is further validated on a flexible MoS top-gate transistors and logic circuits, demonstrating its potential for scalable and large-area high-performance 2D electronics.