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This study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs. By leveraging the floating body effect, this architecture eliminates the need for capacitors, thereby improving integration density and memory performance. Through Sentaurus technology computer-aided design simulations, we compare the PE NS 1T-DRAM device with a conventional NS 1T-DRAM device to evaluate its effectiveness. The results reveal superior retention time (RT) and sensing margin (SM) performance of the proposed PE NS 1T-DRAM device, surpassing the memory criteria outlined by the International Roadmap for Devices and Systems, which requires an RT exceeding 64 ms at 358 K. This enhanced performance of the proposed device is attributed to its extension region, which functions as a potential well for efficient hole storage, as well as the suppression of Shockley‒Read‒Hall recombination. The PE NS 1T-DRAM device also demonstrates robustness to disturbances, maintaining over 89% of its SM and RT under diverse conditions. This superiority is again attributed to its extension region, which minimizes the effects of current flow and electrostatic potential rise. These results highlight the potential of the PE NS 1T-DRAM design for future high-density memory applications.
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http://dx.doi.org/10.1186/s11671-025-04201-1 | DOI Listing |
Discov Nano
February 2025
School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, 41566, Republic of Korea.
This study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs. By leveraging the floating body effect, this architecture eliminates the need for capacitors, thereby improving integration density and memory performance. Through Sentaurus technology computer-aided design simulations, we compare the PE NS 1T-DRAM device with a conventional NS 1T-DRAM device to evaluate its effectiveness.
View Article and Find Full Text PDFNanotechnology
November 2024
Department of Nano Electronic Convergence Engineering, Kyonggi University, Suwon 16227, Gyeonggi-do, Republic of Korea.
In this paper, we propose a doping- and capacitor-less 1T-DRAM cell, which achieved virtual doping by leveraging charge plasma and bias-induced electrostatic doping (bias-ED) techniques in a 5 nm-thick intrinsic silicon body, thereby eliminating doping processes. Platinum was in contact with the drain, while aluminum was in contact with the source, enabling virtual doping of the silicon body into a*-* configuration via the charge-plasma technique. Two coupled polarity gates and one control gate are positioned above the intrinsic channel region.
View Article and Find Full Text PDFNanomaterials (Basel)
January 2024
School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, Republic of Korea.
Micromachines (Basel)
May 2023
Department of Electrical Engineering, Korea University, 145 Anam-ro, Seoul 02841, Republic of Korea.
Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated.
View Article and Find Full Text PDFNanoscale Res Lett
February 2022
Department of Convergence IT Engineering and Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.
Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (V) and anode-cathode voltage (V) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized V of - 0.
View Article and Find Full Text PDF