3ω correction method for eliminating resistance measurement error due to Joule heating.

Electrical four-terminal sensing at (sub-)micrometer scales enables the characterization of key electromagnetic properties within the semiconductor industry, including materials' resistivity, Hall mobility/carrier density, and magnetoresistance. However, as devices' critical dimensions continue to shrink, significant over/underestimation of properties due to a by-product Joule heating of the probed volume becomes increasingly common. Here, we demonstrate how self-heating effects can be quantified and compensated for via 3ω signals to yield zero-current transfer resistance.

Atomic Layer Deposition of Ruthenium with TiN Interface for Sub-10 nm Advanced Interconnects beyond Copper.

Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing.

Nanotube substituted source/drain regions for carbon nanotube transistors for VLSI circuits.

Aggressive scaling of silicon technology over the years has pushed CMOS devices to their fundamental limits. Pioneering works on carbon nanotube during the last decade possessing exceptional electrical properties have provided an intriguing solution for high performance integrated circuits. So far, at best, carbon nanotubes have been considered only for the channel, with metal electrodes being used for source/drain.