An Electrode Design Strategy to Minimize Ferroelectric Imprint Effect.

The phenomenon of ferroelectric imprint, characterized by an asymmetric polarization switching behavior, poses significant challenges in the reliability and performance of ultra-low-voltage ferroelectric devices, including MagnetoElectric Spin-Orbit devices, Ferroelectric Random-Access Memory, Ferroelectric Field-Effect Transistors, and Ferroelectric Tunnel Junctions. In this study, the influence of electrode configuration in different device architectures are systematically investigated on their imprint effect. By tuning the work function of LaSrMnO (LSMO) electrodes through oxygen pressure during deposition, precise control over the built-in voltage offset (V) in ferroelectric capacitors are demonstrated.